Re: Generating a constant-rate synchronous data stream: classical control loop?

Tim Wescott wrote:

I already told him that. He didn't bite. I suspect he's working to one
of those "You know what I mean" specs.

Jerry
--
Engineering is the art of making what you want from things you can get.
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Jerry, Tim,

thanks a lot for your suggestions.
I think I'll have the hardware available to perform some tests next
week. I'm going to adopt the classical control loop based on PI
controller.
In the meanwhile a couple of coworkers are testing a little bit
different approach. As soon as I get their results, I'll provide more
details about it.

Regards,
llandre

Jerry, Tim,

thanks a lot for your suggestions.
I think I'll have the hardware available to perform some tests next
week. I'm going to adopt the classical control loop based on PI
controller.
In the meanwhile a couple of coworkers are testing a little bit
different approach. As soon as I get their results, I'll provide more
details about it.

Regards,
llandre

As anticipated, we tested two different configurations.
Both configurations:
a) uses as error signal the difference between current FIFO level and
half level
b) increase/decrease FIFO read clock speed by acting on a NCO.
They differ with respect to the type of controller that process the
error signal and acts on NCO.

= Configuration #1: controller is a IIR filter =
This configuration reaches steady-state in few seconds but exhibits a
relatively large steady-state error.

= Configuration #2: controller is PI =
Transient is very long (90 minutes or so) but steady-state error is
very small (1/4 with respect to configuration #1).

The achieved performances of conf. #1 are enough to match system
specification, however I think that it is possible to shorten
transient of conf. #2 by fine-tuning P and I term constants while
keeping small steady-state error.

Regards,
llandre