S/W Eng Asks For Intuitive Explanation Of Logic Diagrams Using C Code (And, Or, Min/Max Li...

Chris L wrote:

sci.logic is not a good newsgroup for this. It is concerned with a much
more abstract form of logic than computer hardware.

I came to the same problem from the opposite direction, as an
experienced programmer and software architect in a job where I needed to
communicate with hardware logic designers.

"And" and "Or" map directly to the C operators && and || when given
inputs that are all either zero or one. I'm not familiar with Min/Max
Limiter. Delays don't really make sense in software, other than hardware
simulators that model a clock. To make sense of them, you have to think
of mappings between the state on e.g. one positive clock edge and the
state on the next positive clock edge.

You may find it helpful to learn a hardware description language, such
as Verilog or VHDL. They are programming languages that can be used to
write hardware. That is, they have a subset that can be compiled to a
gate list.

I liked "Digital Design: Principles & Practices" by John F. Wakerly.
However, it shows boolean equations for gates, rather than C. Your
mileage may vary.

Patricia

Patricia Shanahan wrote:

I fell in love with VHDL 8/9 years ago, so I photocopied a few of the
common books. I basically felt that VHDL is a different programming
style just like Object Oriented Programming is a different style.

I'll find my stash of papers over the weekend. But, I have to humble
myself and say I admit that I had difficulty using VHDL!  My forte is
programming in C etc, but I noticed VHDL goes way way way beyound my
simple notion of what programming is. With VHDL, you simulate hardware
that's the miracle! And, I was only briefly exposed to electronics 10
years ago and probably do not have the experience required. I did use
VHDL in a few very small projects. I'll try tomorrow, I promise!

Thank you,
Christopher M. Lusardi

Chris L wrote:

For individual elements and small collections, truth tables are a good
description. http://www.google.com/search?q=truth+table  For larger
collections, Karnaugh maps are sometimes helpful. (I've even used them
to simplify spaghetti code.) http://www.google.com/search?q=karnaugh+map

Jerry
--
Engineering is the art of making what you want from things you can get.
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Jerry Avins wrote:

But, what is the truth table for a Min/Max Limiter, One Frame Delay,
and integators with variable gain?

Thanks for the memories,
Christopher Lusardi

Chris L wrote:

Limiters and integrators are analog devices, not generally referred to
as gates and not amenable to digital design techniques. Digital delay
elements are usually flip-flops, and incorporated into analyses in a
variety of ways.

jerry
--
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯

@p79g2000cwp.googlegroups.com:


 

Those are funny terms.  For one-frame delay, try looking up D-flip flop.
The limiter and the variable gain integrators really aren't within the
purview of Digital Logic.  An integrator can be simply approximated by a
running sum scaled by the sample period.  You can also use a Simpson's
Trapezoidal Approximation for the integral, but often the sum is good
enough.  As to the variable gain part, try using a simple multiplication.

The Min/max limiter should be easy to implement with a couple of if
statements.


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Scott
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