Threaded View
Subject
John Larkin posted on March 29, 2010, 12:11 pm
I'm designing a gadget that uses an ARM uP, with 12-bit mux'd ADC and
a 10-bit DAC, to essentially make a current and voltage regulated
power supply. The ADC will measure voltage and current and the DAC
will control a fairly soft source-follower series-pass mosfet. The
customer load could be most anything.
I think it would be time-effective to simulate the control loop while
the PC board is being fabbed, so we don't have to play with dynamics
as much in the critical delivery path.
I can simulate it as an analog loop using LT Spice, as I'm familiar
with that and could get it done quickly. It would be handy if I could
also use the same model in digital mode, which would add sampling
delays and maybe even quantization.
Any thoughts on how to do this?
I note here that more and more formerly-analog control loops, things
like switching power supplies, motor drivers, power amps, will be
going digital in the future. Some of the ARM chips are selling for
under a dollar. Analog parts will, I think, increasingly be used for
things like amplification, and less for computation.
John
Vladimir Vassilevsky posted on
Re: simulating a digital control loop
John Larkin wrote:
You can simulate digital loops in the analog simulator quite accurately.
The main problem is how to do delay by one sample. In the simple
cases, this can be simulated as 1-st order phase shifter; you may need
better approximation as you get closer to Nyquist. Another way to
simulate digital circuit is by switched capacitor sircuit (beware of
convergence problems).
I've done it both ways; it is possible to get reasonably accurate
results if you know and understand the properties and limitations of
both analog and digital methods.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Re: simulating a digital control loop
On Mon, 29 Mar 2010 11:26:39 -0500, Vladimir Vassilevsky
I'd be happy with a 1 millisecond risetime, and can run the loop
iteration ballpark 50 KHz, so my integration constants will be small.
Given that, I can probably ignore sampling issues or, as you suggest,
just throw in something like RC delays to approximate the effects of
sampling.
Simulating quantization would be interesting. I'll effectively (maybe
even on purpose) be dithering the ADC and especially the DAC to more
bits than they actually have.
Hmmm... if I put an analog lowpass between the ADC and the mosfet
(it's there already to deglitch, and I can play with the tau) the PID
loop sort of dithers the DAC all by itself. And that dithers the ADC.
All for free.
John
Muzaffer Kal posted on
Re: simulating a digital control loop
On Mon, 29 Mar 2010 09:11:48 -0700, John Larkin
You can use ptolemy or matlab. Either can do the job you're trying
pretty well.
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
Tim Wescott posted on
Re: simulating a digital control loop
John Larkin wrote:
For analysis with a linearized plant see chapter 7 of my book:
http://www.wescottdesign.com/actfes/actfes.html .
If you're trying to simulate the loop with all of it's nonlinearities
then Vladimir's suggestion of a one-cycle delay sounds smart. I don't
know if there's a reasonable way to add quantization, though. You may
want to consider a sample-and-hold circuit to simulate the action of the
DAC and of any internal integrators instead of the delay; in theory it'd
be more accurate.
I wish that someone made an easy integration between some C-like
scripting language and a circuit simulator (BTW: if it costs more than a
new car it's not easy). Then you could implement your control algorithm
in something resembling its native form, and still get a "real" circuit
simulation.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Fred Bartoli posted on
Re: simulating a digital control loop
John Larkin a écrit :
It can easily done with spice.
The software delay can be modeled as a TLINE provided it is constant in
your system.
For switchers you model the switch as an averaged one (continuous
model). The sampling action is modeled by a 2 poles TF (look at Ridley's
paper "Accurate and practical small signal model for current mode
control", or I can try to dig in one of my previous HDs).
With good modeling you can have average transient and AC (loop gain,...)
simulations which are real close to the actual circuit.
That won't give you quantization though, and I guess this can't be
modeled as with sigma delta since you have a first order loop and
probably an almost constant signal.
Maybe, but I never tried this, you can discretize the loop (only for
transient analysis) with use of B "arbitrary sources" within which you
use some integer part function. I don't know whether LTspice support B
sources, but you should find something equivalent...
--
Thanks,
Fred.
Re: simulating a digital control loop
Fred Bartoli wrote:
Quantization looks like infinite gain, though, so unless it is wrapped
inside of a sampled-time section it'll really slow down -- or completely
crash -- the simulation.
You can analyze fairly well for quantization by treating it as noise at
the magnitude of the quantization, and the worst possible frequency.
Just inject a signal at the quantization point, do a frequency sweep to
figure out the sensitivity of the output to the quantization, and take
the worst spot.
Quantization always seems to seek to do the most damage possible, so
treating it as worst case isn't paranoid. In this case, it really is
out to get you!
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Re: simulating a digital control loop
Tim Wescott a écrit :
It's been a while I've looked at this but IIRC it's only one bit
quantizer that have infinite gain. Multibit quantizers, as I guess John
will use since he has plentiful bits ADC/DAC, have unit gain.
I once used an ARM with 12b ADC/DACs to build a low OSR SD converter
with real high resolution at almost no cost (the ARM was mandated for
other things). Of course it wasn't more linear than the DAC on large
signals, but the app was OK with that...
--
Thanks,
Fred.
Re: simulating a digital control loop
Fred Bartoli wrote:
At the point of the quantization step the input moves an infinitesimal
amount, and the output moves a finite amount. That's an infinite gain.
With a 12-bit device, it happens 4095 times, instead of once.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Jerry Avins posted on
Re: simulating a digital control loop
Tim Wescott wrote:
It really plays havoc when computing a simple "derivative".
Jerry
--
Discovery consists of seeing what everybody has seen, and thinking what
nobody has thought. .. Albert Szent-Gyorgi
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Re: simulating a digital control loop
Derivatives usually cause more trouble than they do good. My "PID"
controller will almost certainly have D=0.
John
Re: simulating a digital control loop
John Larkin wrote:
I quibble with that 'usually'. "Very often", perhaps, and the trouble
that's caused is often bad enough to make you shudder every time you
think about turning up the derivative gain.
A judicious amount of derivative, in the form of a lead-lag with closely
spaced zero and pole, can often do a world of good -- when it's not
snarling you up in 2nd-order effects, of course.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Re: simulating a digital control loop
wrote:
One way to avoid overshoots is to pre-shape the demand input, like
using an adaptive slew limit or some such. I've done that in steamship
throttle controls where you don't want to stress the plant too much,
and NMR temperature controllers where a modest overshoot can poach
some enzyme that a hundred rabbits died to make.
John
pnachtwey posted on
Re: simulating a digital control loop
On Mar 29, 11:53 am, John Larkin
Many systems don't require a derivative gain. It depends on the
number of poles in your plant and we have no idea what you are trying
to do.
I am a big believer in derivative gains since I must tune under damped
systems. The trick is a have very fine resolution feed back that is
almost noise free or a good model. I would use 16 bit analog feedback
devices to get the finer resolution. I was just at a site where I
used the second derivative gain and it was necessary.
Sometime a low pass filter on the output helps too. If you are clever
you can calculate the gains and take the low pass filter into
consideration. This is better than trying to tweak each gain one a
time along with the output filter.
Do you have excess CPU time?
Peter Nachtwey
Re: simulating a digital control loop
On Mon, 29 Mar 2010 15:31:02 -0700 (PDT), pnachtwey
This is my VME module, with 12 channels of 4-20 mA isolated outputs.
Each channel has its own ARM with a 12-bit ADC and a 10-bit DAC. The
ADC will measure the voltage drop across a shunt resistor, to get loop
current, and also our terminal voltage. The DAC drives a series linear
mosfet to regulate output. It will behave like a constant-voltage,
current-limited power supply, in that the user can program current and
voltage and it will operate in the appropriate mode, depending on the
load.
It's a 100 MHz 32-bit cpu, and the fastest I can digitize the pair of
inputs is 100 KHz, and I could run the loop at 50 or even 25 KHz, so
there should be tons of cpu cycles available.
John
Re: simulating a digital control loop
John Larkin wrote:
You may be surprised at how quickly you can use up 1000 CPU cycles.
--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Re: simulating a digital control loop
wrote:
Depends on the C compiler, I guess. If I were doing this in assembly
on a 68332 with a 20 MHz clock, I'd have no problem doing this PID in
10 microseconds. You'd think a 100 MHz ARM, with a single-cycle
multiply, could match that.
This will be interesting.
John
Re: simulating a digital control loop
John Larkin wrote:
This is not a lot. The loop cutoff frequency can hardly be done higher
then 1/(6 x total delay in the loop), so if you run at 25kHz, it is
going to be 4kHz or so. You probably want at least 20dB of feedback, so
400 Hz it is; unless real fancy feedback arrangements. Pretty slow.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Re: simulating a digital control loop
On Mon, 29 Mar 2010 19:19:47 -0500, Vladimir Vassilevsky
I could tolerate a 1 millisecond risetime, which is in fact in the
ballpark of 400 Hz. If I run at 50K, things should be OK. I can maybe
run at 100K, which gives me 1000 CPU cycles per whack. This is a
32-bit machine with a single-cycle multiply.
John
Jan Panteltje posted on Site Timeline
- » Engineering Vibration 3rd Edition Inman Solutions Manual
- — Next thread in » Industrial Control Group
-
- » Why is a pole called a pole?
- — Previous thread in » Industrial Control Group
-
- » Measurement validation for process signals
- — Newest thread in » Industrial Control Group
-
- » Re: shop press
- — The site's Newest Thread. Posted in » General Metalworking
-
XML Sitemap