Phase Margin Question for Phase Locked Loops

I don't know how you're adding things up, but if you're getting 253 degrees of phase shift without an inverter then you're going to be unstable.

Are you sure that your program isn't taking the VCO phase shift into account? The VCO is also going to have gain that varies with frequency, so finding the loop filter's unity gain frequency is pretty meaningless without knowing the VCO's gain.

Unfortunately the Barkhausen criterion, while it's dandy for determining that you _are_ oscillating, isn't sufficient to determine if you're _not_ oscillating. For example you can have 180 degrees of phase shift before you hit the inverting terminal of your summation junction, with a gain that exceeds 1, and still have a perfectly stable system -- it's only if that gain goes _down_ that you'll have problems. The only way to really tell is with a Nyquist plot, and even then you have to know if you have any unstable zeros (you almost certainly don't).

And to answer your question, no.

However any multiplying phase detector, such as a mixer or an XOR, have an output vs. phase characteristic that is either triangular or sinusoidal in phase, and has a 0-degree phase shift segment as well as a

In article , Tim Wescott wrote: [...]

You can also tell looking at a Bode plot. The place where the phase matters is where the gain curve drops below unity for the last time. If the total phase shift at that point is less than 180 degrees, the line on the Nyquist plot can't enclose the -1 point.

I assume you mean "alway covered against an extra invertering" here.

There is another gotch to watch out for. In the case of a multi-pole filter, the multiplying phase detector can lead to situations that are unstable for large phase errors but stable for small errors. If this PLL is being used to track a moving target, and uses a muliplying phase detector, check that the system is stable for reduced gains. If it isn't, some modulation frequencies may cause early loss of lock.

They detect the phase difference. If the inputs are a(t) and b(t) then the phase difference is:

a(t) - b(t)

The -ve sign in front of b(t) is where the 180 degrees comes from.

a(t) = reference b(t) = vco

frequency,

meaningless

Well, you bring up a good point. I'm not yet able to simulate a VCO in ADS.

So at this point, i'm simulating only the loop filter, which is fairly easy for anyone really, and then defining the phase margin as how far the phase shift is from 90 degrees.

So the question is: is assuming the phase shift of the 1/s integrator of the VCO as always being PLUS

determining

I believe the Barkhausen criterion is only good for when [GH]=1, or at least very close to one. Even if you look at the closed loop formula> G/(1+GH) you can see that if [GH] is greater than one, that the closed loop gain gets smaller, not larger, whether you have positive OR negative feedback!

Slick

The VCO is 1/s and accounts for 90 degrees. The loop filter has another integrator, and that accounts for another 90 degrees. So the closed loop would be unstable where the open loop gain = 1, except this is explicitly why the zero is put into the loop filter: to pull phase back from 180 degrees where open loop gain crosses 1.

That's true. So would it be safe to just add 90 degrees to the phase shift of the loop filter, at the open loop gain=1, and then subtract

Or in other words, is the phase shift of the VCO always +90 degrees across the band? This seems to be the assumption.

Slick

Mathematically safe, but 90 + 90 - 180 = 0, and that's exactly the phase margin you'd have.

You need to brush up on your control theory. An integrator has a transfer function of k/s, when you evaluate this at a sinusoidal frequency it always has a phase shift of 90 degrees -- but most people refer to it as -90 degrees, because you're evaluating k/(j w), which is equal to -j k/w, which has -- negative 90 degrees phase.

people

Opps! Yes, the VCO is 1/s, so it's like a capacitor, with a -90 phase shift.

Well, i got +163 degrees in simulation, so that would be 163-90=73. 180-73= 107 degrees phase margin. Quite a bit from 45 degrees.

SLick

What were you using for a filter? In general a low-pass filter will have negative phase shift. I find it hard to believe that a practical PLL loop filter would _add_ phase margin -- you're generally engaged in a battle between reducing phase detection noise and keeping a stable loop.

For some reason your postings show your messages as going to sci.engr.control, and our replies go there, but your postings don't.

I read in sci.electronics.design that Tim Wescott wrote (in ) about 'Phase Margin Question for Phase Locked Loops', on Mon, 3 Jan 2005:

Maybe his ISP doesn't carry that newsgroup.

practical

Single-ended input inverting integrator op-amp.

We get -90 from the feedback capacitor, but then

4.7uF

-----33k---{}---- ] ] ] ] ] ] ] ]

---66k---] - ] ] ] ] ] ] ]---------- Ground---] + ] ] ] ] ]

This is a simplified version, but if you put it in your simulator, you should get a positive phase shift at around 10Hz.

Slick

engaged

stable

That other ascii diagram didn't turn out, so let's just say it's a single-ended input inverting integrator op-amp, your garden variety active pll filter, with input R1=66k, feedback R2=33k, and feedback C1=4.7uF ("+" input grounded).

We get -90 from the feedback capacitor, but then

This is a simplified version, but if you put it in your simulator, you should get a positive phase shift at around 10Hz. Slick

You need to use a fixed-width font and avoid tabs to make ASCII art work.

An inverter doesn't always solve a phase problem. What comes out of an integrator is a quarter cycle delayed, whatever polarity you arrange for it. You can think of 90 degrees and an inversion as -90 + 180 = +90 degrees. You can just as well think of it as -90 -180 = -270 degrees.

Jerry

We need the inverter for our design in this case, otherwise our phase margin ain't enough.

And i don't see too many integrating op-amp loop filters that aren't inverting by design anyways.

Slick

That just won't work. Putting an inverter into your loop to "add phase margin" is like driving backwards fast so you won't exceed the speed limit -- it's correct in a sense, but you'll just get busted worse.

If you have a loop with negative feedback at DC, which is what you need to get all the nice benefits of, well, _negative_ feedback, and your phase margin isn't right so you put an inverter in it, then you have _positive_ feedback, with all it's nasty disadvantages.

It already does work!

You've only designed with passive, single ended filters?

Most active PLL filters are inverting.

Slick

The up/down steering logic between the phase detector and the charge pump is reversed to cancel the inversion in the active loop filter.

F(s) may be -A*(s+B)/s but kPD is really -kPD The negative signs cancel out.

The open loop gain is

G(s) = kPD * A*(s+B)/s * kVCO/s

i.e. two poles at the origin and a strategically positioned zero.

The phase is +180 until the zero kicks-in. The phase then gradually drops to +90. Phase margin is how far below 180 it has fallen, at the frequency where magnitude of G passes through unity.

...

That's fine. Still, you don't understand why. An inverter between the error signal and the loop is necessary to achieve negative feedback. The inverter provides 180 degrees and the integrator by itself eats half of that, leaving 90 degrees phase margin, the best one can do. Other roll-offs decrease the phase margin even more, putting some ringing into the response. 40 degrees of phase margin usually allows a very acceptable overall response.

...

That's easily changed without altering their characteristics. All feedback circuits need inversion to be stable. It's the additional phase shift between DC and the zero-dB frequency that matters.

Jerry