I'm wondering if it's viable to lay out high speed CMOS logic ("high speed" meaning 32MHz clock, 1-5nS edges) on two layer FR-4 62 mils thick as usual, but omitting the ground plane. You give priority to power and signals, then you glue self-adhesive copper sheet to the bottom of the PCB, driving small brass nails through the ground vias and soldering them in place.
I would expect the soldermask + adhesive to provide insulation, if I tent the vias.
I'd route signals on top as usual, use the bottom layer for power, and then you'd have a higher plane to plane capacitance, and I'd assume the signals would "see" the ground plane and the power plane on more or less the same height and use both as the reference plane.
Reason: 2 layer PCBs are much cheaper to get built than 4 layer!
Make sense, or it's lunacy?