Hi everybody. I need to implement in FPGA a system that generates an output constant- rate synchronous data stream whose data rate has to be equal to the average data rate of an input data stream. The system works like this. Input is a synchronous 8-bit data stream. This stream is provided with a 12.5 MHz clock and a "data valid" signal. This signal gates the input clock, in other words it says when input data are good. This data stream is fed to a FIFO. FIFO write clock is obtained by ANDing input clock with data valid signal in order to discard data when data valid signal is inactive. Output data stream is read by the FIFO. The read clock is generated by a numeric controlled oscillator (NCO). The frequency of the read clock has to be equal to the average frequency of the FIFO write clock. Writes into the FIFO are distributed in bursts. This means data valid is active typically for 6250 consecutive input clock cycles. Then it is inactive for about 3750 cycles. This pattern is usually repeated 3 times. Then we have a long pause of about 30000 input clock cycles where data valid is inactive. The overall pattern is periodic:
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6250 valid bytes fed into FIFO 3750 invalid bytes (discarded) 6250 valid bytes fed into FIFO 3750 invalid bytes (discarded) 6250 valid bytes fed into FIFO 3750 invalid bytes (discarded) 30000 invalid bytes (discarded)---------------------------------------
6250 valid bytes fed into FIFO 3750 invalid bytes (discarded) 6250 valid bytes fed into FIFO 3750 invalid bytes (discarded) 6250 valid bytes fed into FIFO 3750 invalid bytes (discarded) 30000 invalid bytes (discarded)--------------------------------------- ...
I was thinking about using a classical PID control loop. The setpoint is equal to half of FIFO size. FIFO size is 512kB so setpoint is
262144. The error signal is current number of bytes stored in FIFO minus 262144. This error signal is fed to PID controller. PID controller acts on NCO by increasing or decreasing FIFO read clock. PID controller is supposed to work in order to make the error to go to zero, that is data count in FIFO is near 262144. This is true if the data are retrieved from FIFO at the same rate at which, on average, data are written into FIFO.One of the concerns I have is about input data steam distribution. Since it is inherently burst-oriented I'm afraid read frequency will oscillates excessively (it will increase significantly during write bursts and will decrease significantly during the periods where input clock is invalidated). So I'm wondering if other approaches are more suitable for this situation (estimators, Kalman filter ...).
Thank a lot in advance for any feedback.