During rising edge OR falling edge of a clock, data are taken once within one clock cycle in an electronic circuit such as D-flipflop. Meanwhile for double data rate like DDR RAM, during rising edge AND falling edge of a clock, data are taken once respectively in one cycle. Am I right?
Does AGP 2x works the same way as I mentioned earlier? How do AGP 4x and 8x card work?
Assuming the 'OR' in the first sentence is exclusive, you are right.
Sure.
QDR (Quad Data Rate) uses two clocks 90 degrees out of phase with each other. Using both edges of both clocks gives four transitions per cycle.
They use "tricks" to generate clocks so that they can sample more frequently, probably the easiest is to use a PLL, however there are pure digital ways to get the necessary clocks. TTYL
Meanwhile for AGP 8x, it uses four clocks?
A tad more complicated than that. Google on the specs.
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