I am interested in a presentation made at the IEEE 30th Annual Multiple-Value Logic Symposium 2000. It was called "Hardware Implementation of Supplementary Symmetrical Logic Circuit Structure' Concepts", abbreviated SUS-LOC. The presenter was Dan Olson of EDO LLC.
I am especially interested in the viability of the SUS-LOC technology, any major competitive technologies, and the long-term prospects for its practical implementation. I have read some background material but my knowledge of MVL is quite limited at this stage. Therefore, I am not in a position to fully appreciate the value of the technology relative to other options.
For convenience, the following is the title and the abstract from US Patent 6,133,754 (2000) assigned to EDO LLC with Mr. Olson as the inventor:
Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)
Abstract
Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater than
1 and n is an integer greater than 0. This structure is called SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC). In circuits incorporating SUS-LOC, circuit branches are realized that uniquely deliver circuit response and output. For some circuits, and due to the operating characteristics of the switch elements, additional circuit elements, or stages, must be incorporated to prevent "back biasing." SUS-LOC is fully active. Only active elements perform logic synthesis and those components not directly related to logic synthesis, such as resistors and/or other passive loads, are relegated the task of circuit protection. The fabrication of r-valued, multi-valued, or multiple-valued logic circuits, designed using the definitions of the SUS-LOC structure can be accomplished with known techniques, materials, and equipment.Thanks for any assistance you can provide.
Steve Roman Houston