anti aliasing filters for digital control loops

Hi
Is it usual to stick an anti-aliasing filter before the a/d conversion on digital control loops? My problem being that phase response of the
anti-aliasing filter introduces a phase delay that can stuff up the closed loop system stability. Or is it just a case of getting the filter design right?
Thanks in advance
Steve Minshull
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Steve Minshull wrote:

The filter design should not be a problem in a well conceived system. For control loops, the sample rate ought to be 5 times the highest significant frequency, and 10 is better. Part of the reason is that it largely solves the aliasing problem. It really doesn't matter if something at 12*Fmax aliases down to 8*Fmax, and there's not much phase penalty in bringing the alias at 2*Fmax down enough so it won't matter.
A less obvious point is processing delay. With critical sampling where Fs is a hair over 2*Fmax, a one-sample delay is a 180-degree phase shift. The way most systems are implemented, you can get a one-sample delay in the A/D and another in the D/A. Filters can add more.
Symmetric FIR filters' delays are half their number of taps. They aren't much use in servos. Servos need filters whose impulse responses are weighted toward the front. They show dispersion -- delay varies with frequency -- but decent phase margin is about keeping the delays small, not about keeping them equal. I call such filters "prompt". The technical term "minimum phase" may be too restrictive. Almost minimum is usually good enough. A quote from Chris Bore (http://www.bores.com /): "... the worst possible design that just meets the specification - almost a definition of practical engineering"
With a high sample rate, the critical frequencies most filters are low compared to it, and IIR filters excel at that. Even impulse-invariant designs work well and may be simpler than the more versatile biquads.
I'm cross posting to comp.dsp so others can critique me and pick up where I left off. I'll be away for a while. Good luck!
Jerry
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Jerry Avins wrote:

Yes to everything here, with the added comment that I have found a single-stage comb filter to be very useful in anti-aliasing. The idea is to sample at 4, 8 or 16 times your desired control rate, add up all the samples and shift to right to normalize, then go ahead and control. This is an FIR filter, and it does add delay, so you have to compensate by keeping your control sampling rate up.
The really nice thing about this scheme is that the comb filter has big wide notches at the controller's sampling rate and all it's harmonics. You may have aliases that come from noise at (n + 1/2)Fs, but when it gets applied to the controller it's at Fs/2, where either your controller or your plant isn't going to pass much energy. What you _won't_ have is aliases that come out of the filter very close to DC, which is usually where you can least afford aliasing problems.
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How can you use a digital filter for anti-aliasing?
Rimmer
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Rimmer wrote:

The same way you use an analog one -- filter out unwanted spectrum at the alias frequencies before sampling (or in this case before downsampling).
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To clear up confusion, this addresses aliasing that might be introduced by decimation in time. The assumption is that your original sampling is fast enough so that you can ignore any aliasing effects at that stage.
Scott
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Scott Seidman wrote:

Not exactly, even though that would be enough. (One likes to sample 5 to 10 times the Nyquist rate in a servo system. A bit of garbage above the unity-gain frequency can be tolerated. Etc.) The scheme also guarantees null at those frequencies where the strongest and most troublesome aliases would occur. It isn't free: to end up with 10x samples and also use 16x anti-alias "filtering", the original sample rate has to be at least 250 times the servo's unity gain. A successive-approximation converter is needed to keep the latency low.
At least that's how I see it. I had not thought of it until Wescott described it yesterday.
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Thanks for all the help. My problem was having a too low sampling frequency. The end application is a digitally controlled buck converter for charging batteries where i'll be sensing current and voltage and then i can vary the charging sequence in software (either in voltage control or current control). This probably isn't the best way of going about business but it's purely an educational project in my summer holidays.
I was planning on using a 18 series PIC microcontroller (as i have the development hardware+software) which can output a PWM of upto 40kHz at a 10 bit resolution. Now presumably thats the limit on my sampling frequency as I don't see any point in sampling more often than I can update the output.....am I right? So with a 40kHz sampling frequency do I need to design my buck converter with a open loop bandwidth of ~4kHz?
It would also be nice to get a simulation of the system running in Simulink (to aid my understanding at make the right design decisions). I realise that you can model the a/d&d/a action as a zero order hold function but in this sytem the input into the plant's TF is a PWM signal. Any ideas on what i should do here?
Thanks Again
Steve Minshull

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Steve Minshull wrote:

You As you can see from Tim Wescott's suggestion, you might want to take several samples for every one you end up using. Still, 40 KHz may be higher than you need.

That's a good idea. A lower frequency is probably adequate, and would mean more time for the computations.

Not from me! With luck, from others.
...
Jerry
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No. You don't need to match the rate of the control loop to your PWM signal, and life will be incredibly difficult if you try. The PWM of 40kHz can be COMPLETELY independent of the rate of the control loop!!
Set up the PWM frequency at 40 kHz according to the PIC. This is all handled by the PIC hardware (assuming that the 18 series you've chosen has hardware PWM). Then, use a timer to control the rate of the control algorithm. The best way is to set a flag with the timer ISR, and do all your calculations outside of the ISR when the flag goes high (then reset the flag of course). Each pass through the control algorithm, adjust the duty cycle of the PWM.
For example, assume that 1kHz is a sufficient rate for your buck converter (and that's probably 2 orders of magnitude faster than you need). Now let's say your control algorithm calls for a 35% duty cycle. Set the duty cycle at 35. You'll then get 40 pulses of 35% duty with a PWM set to tick at 40kHz. The next algorithm check, you get 26% spit back. Set the width, and repeat every msec.
If we had to run our control loops at the PWM rates we sometimes need, we'll all go crazy.
Scott
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Steve Minshull wrote:

Without writing custom blocks or having subsystems sampled at very high rates your best bet is probably to just output a continous value and don't try to PWM it. Unless you pour an incredible amount of energy into it you can't get a simulation to match reality all that exactly -- at some point it's cheaper to just build a board and try it out.
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Tim, the 18-series has hardware PWM. You set it up, and it goes at whatever frequency you tell it to. The control rate can be orders of magnitude slower.
Scott
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Scott Seidman wrote:

Sorry, I wasn't clear -- I was only addressing how to simulate it, not how to make it work in practice. In practice you use the PWM, most certainly. Given the amount of ripple the PWM will induce, it's probably a good idea to try to sample synchronously with the PWM, if possible, however.
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high

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>>>at some point it's cheaper to just build a board and try it out.
>>>
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Hi.
Again thanks for the help.
With regard to the control loop bandwith. The transfer function (output volts vs duty) i have got from state space averaging is: Vo/d = Vi / ( LC (s^2 + (s/RC) + (1/LC))). So the undamped natural frequency fn = 1/(2pi * root(LC)). Am I right in thinking that I size L and C to give me the required controll loop bandwidth? If so then the inductor/capacitor size seems rather large for a 10Hz bandwidth. The biggest inductor i can find (RS/Farnell) for the max current of 2A is 680uH so I'm a bit limited here without designing my own inductor.
Steve Minshull

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You tune things to the PWM frequency, not the control loop frequency.
Look at some pseudo code
main(){ set PWM frequency to 40K set PWM duty cycle to 50%
while (1){
     if timerflag=1 {          sample the voltage and/or current          calculate next PWM duty cycle          set PWM duty cycle          timerflag=0      }
}
} timer_isr(){ timerflag=1 timercount=timercount+offset (to give you 1kHz control loop) }
Whenever the timer rolls over (goes from ffff to 0) the interrupt service routine gets triggered, setting the timer flag, and then adding any offset to the count register that you need to give you the control rate you need. Thus, your main loop sits there doing nothing until the timer rolls over, but your hardware PWM is ticking away at 40K, at whatever duty cycle it was last set to.
The only waveform your buck converter sees is the PWM switching at 40K. This is the frequency that you select all your components for. The control loop is merely how often you change the duty cycle.
Scott
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Hi
Thanks, I understand the difference between the PWM freq and the control loop sampling frequency. I understand you can choose the inductor size to get a certain current ripple at the PWM switching frequency. I was referring to choosing the inductor size to get the converter bandwidth down as low as 10Hz. I think I may be getting confused in how to work out the loop bandwidth as the sampling frequency should be ~10x this loop bandwitdh. I was assumning the loop bandwidth was determined by the frequency response (bandwidth) of the plant (buck converter) and such i would need a large inductor/capacitor in order to limit the controller bandwidth to 10Hz. Presumably i'm going wrong somewhere?
Steve

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Sample at a rate reasonable to your platform, like 1K. if you need to slow down the loop even more, you can use digital filtering and decimation.
Scott
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Steve Minshull wrote:

> Hi. > > Again thanks for the help. > > With regard to the control loop bandwith. The transfer function > (output volts vs duty) i have got from state space averaging is: Vo/d > = Vi / ( LC (s^2 + (s/RC) + (1/LC))). So the undamped natural > frequency fn = 1/(2pi * root(LC)). Am I right in thinking that I > size L and C to give me the required controll loop bandwidth? If > so then the inductor/capacitor size seems rather large for a 10Hz > bandwidth. The biggest inductor i can find (RS/Farnell) for the max > current of 2A is 680uH so I'm a bit limited here without designing my > own inductor. > > Steve Minshull > No! You size L and C to get the desired ripple and/or transient response. The only thing the filter has to do with the control bandwidth in this case is that you won't have good transient response -- but for charging batteries that's not going to be a big issue.
You'll be limited by the PIC's ability to sample, which will limit your bandwidth. I'd choose a sampling rate, then see what I could tune the PIC up to do. You will, of course, want to have a PID controller on the PIC to get good DC accuracy (depending on your exact driver topology you may only need an integrator, in this case).
See http://www.wescottdesign.com/articles/pidwophd.html for guidance on writing the software, if you need it.
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Steve Minshull wrote:

If you want to respond quickly to things like an output short circuit, you need a fast current control loop, though it can be crude and sloppy. The fast possible way to control current is cycle at a time. This might be as simple as a proportional only feedback loop that samples the current once per PWM cycle (at the time you would expect the current to peak, just as the PWM output is turning off) and alters the PWM duty cycle once per PWM cycle, to correct the current on the next cycle toward the current setpoint. This gives you the ability to react to over current conditions before any damage is done, even on a short. The output filter inductor is the only filtering component involved in this process.
The setpoint for this simple, high speed loop would be the output of a much slower voltage control loop that probably incorporates both proportional and integral effects, but in the case of a battery charger may have a droop effect that allows the integrator to be satisfied with a voltage somewhat less than the voltage setpoint, and the amount of this "somewhat" is proportional to the output current. The tuning of the voltage loop gain and integral time sets its response to a voltage error, since the battery is the main filter component that smooths the voltage. The voltage measurement should be low pass filtered enough that whenever it is sampled, the current ripple from the PWM filter inductor is averaged out over at least a few ripple cycles. I doubt you need an output filter capacitor, unless you want the regulator to be stable with no battery connected.
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