anti aliasing filters for digital control loops

The filter design should not be a problem in a well conceived system. For control loops, the sample rate ought to be 5 times the highest significant frequency, and 10 is better. Part of the reason is that it largely solves the aliasing problem. It really doesn't matter if something at 12*Fmax aliases down to 8*Fmax, and there's not much phase penalty in bringing the alias at 2*Fmax down enough so it won't matter.

A less obvious point is processing delay. With critical sampling where Fs is a hair over 2*Fmax, a one-sample delay is a 180-degree phase shift. The way most systems are implemented, you can get a one-sample delay in the A/D and another in the D/A. Filters can add more.

Symmetric FIR filters' delays are half their number of taps. They aren't much use in servos. Servos need filters whose impulse responses are weighted toward the front. They show dispersion -- delay varies with frequency -- but decent phase margin is about keeping the delays small, not about keeping them equal. I call such filters "prompt". The technical term "minimum phase" may be too restrictive. Almost minimum is usually good enough. A quote from Chris Bore

"... the worst possible design that just meets the specification - almost a definition of practical engineering"

With a high sample rate, the critical frequencies most filters are low compared to it, and IIR filters excel at that. Even impulse-invariant designs work well and may be simpler than the more versatile biquads.

I'm cross posting to comp.dsp so others can critique me and pick up where I left off. I'll be away for a while. Good luck!

Jerry

Yes to everything here, with the added comment that I have found a single-stage comb filter to be very useful in anti-aliasing. The idea is to sample at 4, 8 or 16 times your desired control rate, add up all the samples and shift to right to normalize, then go ahead and control. This is an FIR filter, and it does add delay, so you have to compensate by keeping your control sampling rate up.

The really nice thing about this scheme is that the comb filter has big wide notches at the controller's sampling rate and all it's harmonics. You may have aliases that come from noise at (n + 1/2)Fs, but when it gets applied to the controller it's at Fs/2, where either your controller or your plant isn't going to pass much energy. What you _won't_ have is aliases that come out of the filter very close to DC, which is usually where you can least afford aliasing problems.

The problem you are thinking of happens only in systems that are sampled too seldom, to begin with. If the samples are taken often enough that all frequencies of interest to the control system are well represented by the samples, (more than two samples per period) then the delay of a filter that effectively anti-aliases the samples adds an insignificant delay to all those frequencies of interest. Once the signal frequencies get above the unity gain frequency of the control loop, they have little effect on the closed loop response of the system. So the sampling frequency and anti-alias filter design should be based on at least the expected unity gain frequency of the control loop.

Of course, if the anti-alias filter is very poorly designed and removes frequencies of interest that would otherwise make it through the sampling process well represented, and that are below the unity gain frequency, then it will degrade the loop performance.

The best anti-alias filter is usually the one with the highest roll off corner frequency and the lowest order (lowest group delay) that will do the job of sufficiently attenuating frequencies that are too high for the sampling process to faithfully represent without producing significant aliases. This best fit design will also include assumptions about what amplitude aliases are insignificant compared to other disturbances for the loop, and what amplitudes and frequencies may actually be present that must be filtered. An infinite amplitude case would require infinite attenuation and possibly infinite delay of pass band signals. Good design requires reasonable assumptions.

How can you use a digital filter for anti-aliasing?

Rimmer

Are you referring to division by a power of two by shifting binary values?

Yes! Not just usual; but essential, since without the anti-aliasing filter high-frequency noise will be aliased down into your control bandwidth.

If the filter lag is significant in your control loop, then it implies that your sampling frequency is too low for the application. After all, the phase-lag of the sample-and-hold at the D/A conversion is going to be of the same order!

Kelvin B. Hales Kelvin Hales Associates Limited Consulting Process Control Engineers Web:

yes

The same way you use an analog one -- filter out unwanted spectrum at the alias frequencies before sampling (or in this case before downsampling).

Tim Wescott wrote in news: snipped-for-privacy@corp.supernews.com:

To clear up confusion, this addresses aliasing that might be introduced by decimation in time. The assumption is that your original sampling is fast enough so that you can ignore any aliasing effects at that stage.

Scott

Not exactly, even though that would be enough. (One likes to sample 5 to 10 times the Nyquist rate in a servo system. A bit of garbage above the unity-gain frequency can be tolerated. Etc.) The scheme also guarantees null at those frequencies where the strongest and most troublesome aliases would occur. It isn't free: to end up with 10x samples and also use 16x anti-alias "filtering", the original sample rate has to be at least 250 times the servo's unity gain. A successive-approximation converter is needed to keep the latency low.

At least that's how I see it. I had not thought of it until Wescott described it yesterday.

Thanks for all the help. My problem was having a too low sampling frequency. The end application is a digitally controlled buck converter for charging batteries where i'll be sensing current and voltage and then i can vary the charging sequence in software (either in voltage control or current control). This probably isn't the best way of going about business but it's purely an educational project in my summer holidays.

I was planning on using a 18 series PIC microcontroller (as i have the development hardware+software) which can output a PWM of upto 40kHz at a 10 bit resolution. Now presumably thats the limit on my sampling frequency as I don't see any point in sampling more often than I can update the output.....am I right? So with a 40kHz sampling frequency do I need to design my buck converter with a open loop bandwidth of ~4kHz?

It would also be nice to get a simulation of the system running in Simulink (to aid my understanding at make the right design decisions). I realise that you can model the a/d&d/a action as a zero order hold function but in this sytem the input into the plant's TF is a PWM signal. Any ideas on what i should do here?

Thanks Again

Steve M>> Tim Wescott wrote in

You As you can see from Tim Wescott's suggestion, you might want to take several samples for every one you end up using. Still, 40 KHz may be higher than you need.

That's a good idea. A lower frequency is probably adequate, and would mean more time for the computations.

Not from me! With luck, from others.

...

Jerry

"Steve Minshull" wrote in news:XBDre.12764$ snipped-for-privacy@newsfe5-win.ntli.net:

No. You don't need to match the rate of the control loop to your PWM signal, and life will be incredibly difficult if you try. The PWM of 40kHz can be COMPLETELY independent of the rate of the control loop!!

Set up the PWM frequency at 40 kHz according to the PIC. This is all handled by the PIC hardware (assuming that the 18 series you've chosen has hardware PWM). Then, use a timer to control the rate of the control algorithm. The best way is to set a flag with the timer ISR, and do all your calculations outside of the ISR when the flag goes high (then reset the flag of course). Each pass through the control algorithm, adjust the duty cycle of the PWM.

For example, assume that 1kHz is a sufficient rate for your buck converter (and that's probably 2 orders of magnitude faster than you need). Now let's say your control algorithm calls for a 35% duty cycle. Set the duty cycle at 35. You'll then get 40 pulses of 35% duty with a PWM set to tick at 40kHz. The next algorithm check, you get 26% spit back. Set the width, and repeat every msec.

If we had to run our control loops at the PWM rates we sometimes need, we'll all go crazy.

Scott

Or you can anti-alias with a simple 1- or 2-stage RC filter, if you push your decimation frequency up high enough.

Without writing custom blocks or having subsystems sampled at very high rates your best bet is probably to just output a continous value and don't try to PWM it. Unless you pour an incredible amount of energy into it you can't get a simulation to match reality all that exactly -- at some point it's cheaper to just build a board and try it out.

Tim Wescott wrote in news:11au772evph3k11 @corp.supernews.com:

Tim, the 18-series has hardware PWM. You set it up, and it goes at whatever frequency you tell it to. The control rate can be orders of magnitude slower.

Scott

Sorry, I wasn't clear -- I was only addressing how to simulate it, not how to make it work in practice. In practice you use the PWM, most certainly. Given the amount of ripple the PWM will induce, it's probably a good idea to try to sample synchronously with the PWM, if possible, however.

Tim Wescott wrote in news:11au8uqolr1lhe3 @corp.supernews.com:

Hi.

Again thanks for the help.

With regard to the control loop bandwith. The transfer function (output volts vs duty) i have got from state space averaging is: Vo/d = Vi / ( LC (s^2 + (s/RC) + (1/LC))). So the undamped natural frequency fn = 1/(2pi * root(LC)). Am I right in thinking that I size L and C to give me the required controll loop bandwidth? If so then the inductor/capacitor size seems rather large for a 10Hz bandwidth. The biggest inductor i can find (RS/Farnell) for the max current of 2A is 680uH so I'm a bit limited here without designing my own inductor.

Steve Minshull