Design of anti-alias filter for ADC, with oversampling and averaging

I am trying to design proper anti-aliasing filters for a new hobby
project (digital control of a quad-rotor flying robot - see previous
post for more questions). Here are the specifics:
* My sensors are analog MEMS accelerometers and gyroscopes. I'll have
at least 6 sensors to process, at least initially.
I will be using a microcontroller with 10-12 bit built-in ADCs to
process the sensor data (and implement the control loops)
* I'd like to keep part counts and costs to a minimum (of course)
I'd like to employ oversampling so I can make use of an analog anti-
alias filter with a (relatively) low number of poles
* I'll need to implement a digital filter + decimation to get down to
the desired sample rate
I'd like to average the samples (prior to the digital filter?
although the averager is itself a digital filter) to improve the
effective number of bits of resolution.
So, here are my questions:
* Can anyone recommend a good references for such a design, combining
these elements?
How important is it to use a Bessel filter (linear phase) vs
butterworth (flat passband response) in the analog filter stage?
* What kinds of filter-on-a-chip IC packages exist out there? I think
I'd prefer a switched capacitor or other easily varied type of
configuration (so I can make certain filter changes without altering
Are there any microcontrollers that automate the sampling and
digital filtering processing, with minimal direct intervention? It
looks as if the Luminary Micro ARM line has some hardware sample
averaging capability, for example, but it is not clear if it can
handle 6 simultaneous analog channels.
Thanks in advance
Reply to
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Here is a block diagram of my recommended anti-alias filter for 95% of all digital control loops out there:
_____ | | ---->| 1 |-----> |_____|
IOW, don't do it. The only time you need an anti-aliasing filter is if you have lots of noise at close to your sampling rate. Otherwise, the most significant contribution that an anti-alias filter can have in a closed loop is excessive phase delay.
Having said that, usually when I have the chance I'll oversample the ADC, and hand the controller the sum of the ADC samples in the interval leading up to the controller sample interval. I.e., if I'm sampling the controller at 500Hz, I may sample the ADC at 8000Hz and deliver the sum of the last 16 ADC samples to the controller. This knocks down the ADC noise nicely, and makes a comb filter for any external signal that wants to interfere with my loop. It does add delay, but the delay is minimal for those frequencies that would alias down into my loop.
Reply to
Tim Wescott
Nothing to add to Jerry and Tims fine comments on minimum acceptable rate. Here's my standard counter-reminder to this question: If you go for a high sample rate and use low precision maths (eg. 8 bit) in your processor, check that you don't encounter deadzone in the control algorithms due to mathematical quantisation, particularly with integration algorithms.
Reply to
Bruce Varley

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