In a shameless crosspost on sci.electronics.design, sci.engr.control
Congratulations, and my condolences to ESP. :)
Scanning over the article, it looks good, I've been aware of the
techniques you describe for a while, but it's always good to see
another article on it and some more ideas on how to use it.
Nicely done- I was anxious to see a analytical expression of some sort
for the actual distribution of the noise energy as a function of the
quantizer resolution and the integrator time constant so that this can
be bounded from the start rather than through simulation. Your system
reminded of exactly of an analog circuit for very high resolution analog
voltage to duty cycle conversion using a single chip oa-vref-comparator
combination where the oa integrates the error difference between the
Vin and an output of the comparator switching between Vref and gnd.
Some software engineers can be remarkably averse to that sort of thing
-- editors too.
It doesn't seem to make much difference for a 1st-order system, and
analytical expressions for such a nonlinear system are hard to come by.
I was going to include 2nd-order sigma-deltas in there, but I was not
at all satisfied with my own understanding of them so I'm leaving those
bits out until I know what the f*** I'm talking about.
It sounds like you were just using a 1st-order analog sigma-delta. The
sigma-delta modulator itself is what is used in those itty bitty 24-bit
ADC converters that you can get for instrumentation, they're just
preceded by a 2nd- or 3rd-order loop filter, and succeeded by _lots_ of
digital filtering before the answer gets chunked out to a microprocessor.
Hey, what about taking the extra LSBs and using them to index into a
lookup table full of duty-cycle "waveform" bitmaps? Then you could
approximate higher-order delta-sigmas without actually having to do a
bunch of integrations.
Like 0001001000101010 = duty cycle pattern for 5/16 of a DAC lsb
1011010110110011 = 10/16
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