Something has puzzled me for some time and the question comes back to me from time to time; not that it is important for circuit design, I'm just curious - I have seat-of-the-pants models for valves (Tubes to the Yanks), semiconductor diodes, BJT's and some FET's , but the enhancement mode FET doesn't seem to have a simple explanation. (And, for an engineer, a sound mathematical understanding has to be rooted on some model that one has internalised emotionally)
I can understand the model presented for a depletion mode FET, insofar as there are conduction paths available, but the applied gate bias puts up such a strong electric field that the conduction electrons "cringe" away, but what is the conduction mechanism in an enhancement mode FET? i.e., if there are no free energy levels for conduction electrons to pass through the semiconductor crystal, how does the applied bias create them?
(Somewhat red-faced, I did graduate in electronics 33 years ago! However, a student recently asked me about this and I had to admit to my own ignorance but undertake to find out!)
All JFETs operate in depletion mode whereas MOSFETs can be either depletion or enhancement mode devices. The common feature in depletion mode devices is the presence of a continuous channel of silicon (N or P type, as appropriate) between the source and drain.
In the case of a JFET, the gate is a piece of silicon of the opposite polarity to the channel and, as it is biased, it effectively 'holds' carriers in the region of the channel near the gate. (Some authors say the gate 'grows' into the channel, which is another way of looking at it.)
In the MOSFET, the gate is similar to one plate of a capacitor and as it is biased, it reduces carrier movement in the region near the gate in the channel.
So, in both JFETS and MOSFET, the gate pinches off the channel, controlling the movement of carriers (electrons or 'holes').
The construction of an enhancement mode MOSFET, is not unlike the traditional 'three layer model' used to describe a transistor, with the difference that the gate connection is not made to the middle layer directly but to metal plate isolated from it by a thin layer of polymer. This metal plate extends across the junctions between the three layers but is insulated from all of them.
If a voltage is applied across the source and drain (but not to the plate forming the gate), one of the either S / Gate layer or Gate layer / D junctions is reverse biased and no current flows twixt the source and drain.
When the gate is biased, carriers (of the opposite polarity to the gate layer) are 'attracted' to the region of the gate layer opposite to the isolated gate connection. (In P type material, the electrons are drawn from the region of the gate layer remote from the gate metal plate. In N type material the electrons near the gate metal plate are forced away, into the regions of the gate remote from the plate.)
The bias is increased until enough carriers are present in region near the gate place so that is the same polarity as the source and drain layers. (Some authors describe the polarity of the region being reversed). There is now a channel (similar to that in the JFET, save it has been created by enhancing a carrier concentration) between the source and drain. Varying the bias varies the depth of the new channel and the source / drain current varies accordingly. What is your student stuying for? An engineering qualification or just a hobby?
If that is the case, then it is in the physical construction that my ignorance lay, and not in the electronics. The model I had was of a channel consisting of a single style of doping, and not of 2 junctions back-to-back; hence driving my query as to how energy levels for conduction could be created where none existed before.
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