HBM for ESD test

Dec 05, 2004 3 Replies
B

Hi,



I was wondering if anyone can help me with this. I'm looking for a circuit-block (SPICE model) that generates a current pulse (according to HBM Standard S5.1) that can be connected to one of the inputs of a chip so that I can simulate the behaviour of the ESD protection circuitry. I know what there should be a cap, resistor, risetime of 2-10ns and pulse width of



150ns. But is that enough info for setting up the test bench? Any one has a sample spice deck? The simulations does not have to be very accurate as long as it gives me an idea how to set it up and indication of the behaviour of the ESD protection.

I would really appreciate any help.



Thanks, Janet(beni)


Vote
Twitter Facebook LinkedIn
K

You can time scale. you are missing items on on the source you want. What voltage, need another resistor, and what about negitive spikes?

Vote
Twitter Facebook LinkedIn
D

A charged flash (photo) capacitor will do.I short-circuited once one, and the result was an explosion.It can give you also a shock;the voltage is over

300 volts.It has a dedicated circuit, that makes ac from the battery's dc and raises it to 300 volts, and then dc again.Pretty fascinating thing;I wouldn't suggest though that you open an expensive photo flash unit just to experiment.

-- Tzortzakakis Dimitriïs major in electrical engineering, freelance electrician FH von Iraklion-Kreta, freiberuflicher Elektriker dimtzort AT otenet DOT gr Ï "beni" Ýãñáøå óôï ìÞíõìá news:n0zsd.436952$%k.199657@pd7tw2no...

Vote
Twitter Facebook LinkedIn
C

Quick input from an old IC designer...

ESD events are not accurately simulated in spice. You can easily come up with a HBM source using simple spice elements but the real problem is what happens on the chip. Most of the work that has been done in ESD protection in "the real world" relies on lots of test structures and lab work.

A prime example is a failure mode of NMOS devices where the device goes into localized bipolar snapback and concentrates the energy in a very small area. Solutions to this failure include lots of process specific layout rules, such as contact to gate spacing, minimum junction areas, etc.

If you are really interested is this topic there are some good texts available. What you glean in a news group will not be terribly useful in "the real world".

Best regards,

Cecil Aswell (no numbers > Hi,

Vote
Twitter Facebook LinkedIn

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required