VHDL Simulation-Clock divider takes too long

I'm using altera's max2plus for vhdl synthesis.

I just created a clock divider (counter) that's at 1Hz for a 10mhz clock-- that is, for every billion clock cycles, the clock divider outputs a 1 so I can work with a 1s clock.

My problem is in the simulation of this--- the computer takes a very long time to simulate a mere 4 seconds since it processes every single 10mhz clock cycle. Since I'm using such a divider in a fairly large fsm, there are even more signals in a simulation.

My question is-- is there a way to simulate such a clock divider very efficiently?

Thanks,

Ji Zhang snipped-for-privacy@mit.edu