VHDL extension_pack

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Here's some VHDL I've been working on to support projects on my Digilent board that some of you may find useful. I'll update it from time to time.
Enjoy
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-- author : Michael Bills ( snipped-for-privacy@hotmail.com)
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updated
MB wrote:

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-- author : Michael Bills ( snipped-for-privacy@hotmail.com)
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MB wrote:

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library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
entity rec_and_r is generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_Out : out std_logic); end rec_and_r;
architecture rtl of rec_and_r is constant MAXANDWIDTH : integer := 4;
component and_r generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_Out : out std_logic); end component;
begin
single_and_structure : if (and_width <= MAXANDWIDTH) generate begin U1 : and_r generic map(and_width => and_width) port map( and_In => and_In, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Out); end generate single_and_structure;
multiple_and_structure : if (and_width > MAXANDWIDTH) generate signal and_Sig : std_logic_vector(integer(ceil(real(and_width)/real(MAXANDWIDTH)))-1 downto 0); -- bus for all the registered and gate outputs begin full_width_and_structure : for genLoopVar in 0 to integer(floor(real(and_width)/real(MAXANDWIDTH)))-1 generate begin U1 : and_r generic map(and_width => MAXANDWIDTH) port map( and_In => and_In(MAXANDWIDTH*genLoopVar+MAXANDWIDTH-1 downto MAXANDWIDTH*genLoopVar), clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Sig(genLoopVar)); end generate full_width_and_structure; partial_width_and_structure : if ((and_width mod MAXANDWIDTH) /= 0) and (and_width /= 0) generate begin U2 : and_r generic map(and_width => and_width mod MAXANDWIDTH) port map( and_In => and_In(and_In'high downto and_In'high - and_width mod MAXANDWIDTH), clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Sig(and_Sig'high)); end generate partial_width_and_structure; recursive_and_structure : if and_Sig'length /= 1 generate begin U3 : and_r generic map(and_width => and_Sig'length) port map( and_In => and_Sig, clkIn => clkIn, sysResetIn => sysResetIn, and_Out => and_Out); end generate recursive_and_structure; end generate multiple_and_structure; end rtl;
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library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
entity and_r is generic(and_width : integer); port( and_In : in std_logic_vector(and_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; and_ROut : out std_logic); end and_r;
architecture rtl of and_r is
begin
compProc : process(ClkIn, SysResetIn) constant ones : std_logic_vector(and_In'range) := (others => '1'); begin if (SysResetIn = '1') then and_ROut <= '0'; elsif rising_edge(clkIn) then if (and_In = ones) then and_ROut <= '1'; else and_ROut <= '0'; end if; end if; end process; end rtl;
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library ieee, extension_lib; use extension_lib.extension_pack.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
entity comparator_r is generic(bus_width : integer); port( aIn : in std_logic_vector(bus_width-1 downto 0); bIn : in std_logic_vector(bus_width-1 downto 0); clkIn : in std_logic; sysResetIn : in std_logic; eqROut : out std_logic ); end comparator_r;
architecture rtl of comparator_r is
begin
compProc : process(ClkIn, SysResetIn) begin if (SysResetIn = '1') then eqROut <= '0'; elsif rising_edge(clkIn) then if (aIn = bIn) then eqROut <= '1';     -- output is registered else eqROut <= '0';     -- output is registered end if; end if; end process; end rtl;
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--
-- author : Michael Bills ( snipped-for-privacy@hotmail.com)
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On Wed, 18 Jan 2006 23:38:12 -0700, MB wrote:
<snip 9400+ lines>
Can you please *not* post this every few days?! It looks like decent work (not well commented though) but please! Post it on a web site and point to it. I appreciate what you're doing but I don't want to download it every couple of days! I really can't use it anyway (possible license issues).
--
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Keith wrote:

Keith,
I plan on putting it on opencores when they get a project opened for me. As far as license issues go, use it as you will just like it says in the header of the package. I posted it here for everybody to use. There are freeware tools available. (I use Xilinx WebPack for my dabbling at home). You can use the code for anything you want. I'm not making any claims over anyones usage of it. I would be pleased if someone did use it and I do appreciate feedback on it. What do you feel needs more commenting?
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On Fri, 20 Jan 2006 00:21:20 -0700, MB wrote:

Good deal. PLease refrain from posting it on the Usenet. It's a PITA!

Doesn't work for my employer. You could wrap a Franklin around every line and it wouldn't matter. The fact is that it's code developed with unkown origins and ownership.

Very nice, but most will be afraid to touch it. But my main point is more about the space/bandwidth you're wasting. Do you have to post it so often. Yes, it matters.

Erm, the XIlinx WebPack is *not* freeware. It is licensed for use only with their products.

Perhaps a header with all contents and supported arg oveeloads would be nice. It's huge and I'm not about to go wandering through it to find what I need, even if I could use it.
My main point is that it's not helpfull to keep posting the whole damned thing to a Usenet NG; *ANY* NG.
--
Keith



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