Need help with 80C48 microcontroller

Hi,
I was hoping someone in this ng might be familiar with the older 80C48 microcontorller. It's driving a unit which is controlled via serial
data over a wire pair. The RESET pin is clocking regularly (about 1 hz) and so are all pins on Port 2. Port 1 is stable.
I'm wondering about the RESET itself. My understanding is that it should be clocked once on power up or power down conditions. I think it powers up on a logic high. At least, on my setup, it is driven directly off the output of a NOR gate. One input of that NOR gate is driven off the collector of an NPN transistor. The gate is steady at +5 volts with power on. The other gate input is more complex.
There is a 0.022 capacitor feeding from the NOR gate output back to the other input via a 1 meg resistor. I assume this is an RC circuit to give a monetary pulse to enable the gate. This input is also fed by another NOR gate output, and it's input is fed from the same capacitor via a 100K resistor. The other input for the second NOR is fed via another RC circuit from one pin of Port 2 and two NOR's wired as inverters.
I'm thinking I have a race condition happening. Instead of the RESET doing it's thing during power on, at least one of the input gates must have an unstable condition. So the controller keeps toggling.
Is this a reasonable assumption, or could it be that the microcontroller needs it's normal serial data from the external machine?
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You know they used to program those things with punch cards? Anyhow, try it with just a 1u cap on reset to ground. This will hold the reset low during powerup. Reset during power down is not required if you can deal with some occasional mumbo jumbo on shutdown. It could also be stray power on one those other lines for programming, single step, external addressing, or some other line giving you hassle too. Just make sure to tie everything to the proper level.
--Ryan
www.siliconcybernetics.com

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I used to repair card readers/sorters...what a nightmare.

Basically, what am I looking for on a reset? It's tough to find in-depth information on the 8048. The way my reset circuit is designed seems to output a high on the reset 'after' power is established. Also, some circuits I've seen for reset have a series RC circuit with the RESET pin connected between the R and C and the R connected to ground with the cap to Vcc. . At the instant of power on, Vcc will be entirely across the resistor and the RESET pin will be high. When the cap charges, current thru the R should drop to zero and the RESET pin should be at ground potential.
What should the RESET pin read during steady-state operation? I'm confused about this.

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Lucky for you I was able to dig up my MCS-48 User manual...

A reset will cause ports 1 & 2 to become inputs and the bus to go high impedence.

I am not quite sure what they were doing. Since the reset is active low, they may have been using the R to ground to make the device reset easily when a momentary power failure occurs.

A 200k internal pull up keeps it in the high processor running state.
--Ryan
www.siliconcybernetics.com
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Thanks for your effort.

I needed a bit of luck. :-)

I think it's a time constant circuit to allow Vdd to get up to a certain value. If it resets too quickly, and Vdd isn't up to a certain level, it gets messed up.

OK...so the pull up would be looking for a high level at the RESET pin input. Does that seem right? The RESET is said to be active low. I guess that means when the pull up is connectd to the +5 volts, the other end is a low...probably through a transistor or whatever.

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Actually you gave me a good hint with your MCS-48 manual. I found one on the net and I just have to digest it. Thanks for tip.
On Tue, 25 Nov 2003 21:25:11 -0800, "Ryan Cole"

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I never thought of it being a watchdog timer. I'll look into that...thanks. My concern was that it was also strobing the RESET line. I couldn't see how a controller could work with it's RESET line being strobed at a rate of approximately 1 hz.
I'm trying to troubleshoot the controller circuit out of it's native environment. I have it on the bench trying to run it off a DC power supply. So, it probably wont have a program loaded, unless it has some kind of PROM. That could be causing all sorts of problems, but I don't understand how it can strobe without a program. I'm beginning to suspect the CMOS NOR gate that drives the RESET pin.
I imagine all the internal registers etc. have to be initialized. Or is there a mechanism to initialize the controller through a RESET or other pin?
The driver NOR gate is a 4001 series quadruple 2-input NOR. The 4 NOR's are daisy-chained so one feeds the next. The last one in the chain feeds the RESET pin directly, and the only connection to Port 2 is as the input to the first NOR in the chain. You are suggesting above that the NORs should be strobing the Port 2 pin, but it seems the other way around...that Port 2 is strobing the input NOR gate.
There are 4 RC circuits. Two of them feed from the RESET pin back to the inputs on the 3rd and last NOR in the chain. In fact, the RC circuits are using a common capacitor...something I've never seen before. Their time constants are about 10 to one, with the longest time constant (0.22 micro in series with 2.2 meg) on the NOR input gate feeding the RESET pin ( ~ 0.5 secs). With power on, one input gate of the NOR feeding the RESET is held low by a transistor sensing the +5 volts. The other input gate is driven by the NOR before it and the other RC circuit fed from the RESET pin, through the common capacitor (0.22 micro in series with 100K).
At first, this setup looked to me like a one-shot latch. That's how I've been troubleshooting it anyway. I'll look into what you say about the watchdog, however. Thanks for the tip.
BTW...I posted a schematic to alt.binaries.test for someone else. It's called RESET.jpg. It's Mickey Mouse, but gives a pictorial view of the NOR gate chain.
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