Re: Wireless Hypertek GSE

>The problem is that the input/output circuit of the microcontroller is > > very > >>complex. It is very difficult to predict exactly what it will do at power > > up. > > What happens at power up is specified in the Data Sheet. > Microchip is very clear on this. > We trust Davyfire to spec their matches. > We trust GOEX to spec their BP. > We trust Aerotech to spec their Motors. > But we can't trust a silicone MFG with their spec??

If Microchip made any claims that the I/O pins were glitch free during power up, then yes. Microchip only states that certain registers are set to particular states as the result of a reset condition. I can find nowhere in the data sheet where they state that I/O pins will power up in a glitch free manner.

Figure 17-8 of the 16F628 data sheet is interesting. This figure shows reset timing. Note that the I/O pins are shown as being in an indeterminate state during power on.

There is alot less variability in silicone MFG than any of the other > products I mentioned. >

There is still variability. Particularly in doping levels across the wafer. The exact behavior of a CMOS pair during power up depends on their gate threshold levels which depends on doping levels.

>>There could be a period when the port is in an undefined state. This is > > less > >>likely to occur if your power up is quick. But in the event of a slowly > > rising > >>power supply, very bad things could happen. > > > Current uControllers do not have issues with this. > They have a brown out detect circuit that works on power up as well as later > on. > It will keep the processor in reset till the power is stable. >

From the 16F628 data sheet concerning the power on reset operation:

"A maximum rise time for Vdd is required. See Electrical Specifications for details."

SVdd is specified as a minimum of 0.05 V/ms

Yes, and by the same logic, I see nowhere in the data sheet where they state the I/O pins will power up in a glitchy manner.

Yes, that is true of the Port A and Port B registers. They contain the data that will be output by the output latch, and are in an indeterminate state as shown in Table 14-7. The important part of this table though is TRIS A and TRIS B. These determin if the port pin is input or output. As the table shows they are set as inputs during reset, so it does not matter what values the port registers have. After reset you set the values of the port registers then change them to outputs.

Yes, there is variability. But they will be within tolerance that the process engineer sets. I would be more concerned with failure due to defects. Particles on the mask can 'almost' bridge metal lines. And with ever shrinking geometries the via is more likely to become a failure point than the doping levels.

I was not referring to the power on reset, although I can see how you could have read that in my post. I was talking about the brown out reset. When enabled the chip will remain in reset anytime Vdd is >4V. It does not matter how long it takes to come up to 4V. Then once 4V is reached the power up timer is invoked to keep the part in reset an additional 72ms.\

Thanks for the input RDH8