Rockets and FPGAs

One of my cohorts just sent me this. It's kinda kewl: http://www.designnews.com/article/CA632575.html?nid#37
The emphasis is on the soft-core processor implemented in the FPGA, with
few details of the rocket, but I thought it warranted a mention here.
Doug
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On Tue, 16 Aug 2005 18:46:00 +0000 (UTC), "Doug Sams"

In a similar vein, Cypress have some rocketry related PSoC app notes. http://makeashorterlink.com/?V4D4210AB http://makeashorterlink.com/?I515230AB
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Darren J Longhorn http://www.geocities.com/darrenlonghorn /
NSRG #005 http://www.northstarrocketry.org.uk /
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Your short links didn't work for me....
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David,
Here they are raw and in tinyurl:
http://www.cypress.com/portal/server.pt?space=CommunityPage&parentname=CommunityPage&in_hi_userid=2&control=SetCommunity&CommunityID 9&PageIDA8&r_folder=Application%20Notes&r_title=AN2146%20-%20Standard%20-%20Model%20Rocketry%20In-Flight%20Digital%20Imaging http://tinyurl.com/dq6fm
http://www.cypress.com/portal/server.pt?space=CommunityPage&parentname=CommunityPage&in_hi_userid=2&control=SetCommunity&CommunityID 9&PageIDA8&r_folder=Application%20Notes&r_title=AN2153%20-%20Standard%20-%20Model%20Rocketry:%20Air-Starting%20Rocket%20Motors http://tinyurl.com/bu6bo
Darren,
Thanks for the links.
Looks like these guys don't take themselves too seriously. Nor for the Altera example I posted.
From being in the chip business, I can promise you we'll have a million other applications to support - servers, swtiches, routers, handhelds, medical, et al - before we'll ever get one rocketry application :)
What I find especially funny is the Altera example. It hasn't changed much over the years since they began introducing FPGAs with >1M gates. Basically, they're taking a $400 FPGA and synthesizing in it a $4 microcontroller. I can remember sitting in training sessions for this stuff. What they failed to train us on was how to keep a straight face while we were trying to get customers to see the value of it.
BR, Doug
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On Tue, 16 Aug 2005 22:03:29 +0000 (UTC), "Doug Sams"

I bet. I'm in software myself, but one of my hardware colleagues spotted the app notes and showed me them. Made me think" who are they kidding?" Those PSoCs look quite interesting form the hobbyist though.
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Darren J Longhorn http://www.geocities.com/darrenlonghorn /
NSRG #005 http://www.northstarrocketry.org.uk /
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Doug,     I don't really see any explanation of why this was done using an FPGA so I must assume that it was simply for the exercise. Everything this hardware does can be done by an under $5 PIC. (or AVR, or MSP430, or ...) This would be interesting only if they needed some feature of the FPGA to do something special.
I note that they point out that they implemented a special fixed point divide instruction for their averaging filter. As I have shown elsewhere, it is possible to create a simple filter using _no_ division instructions whatsoever.
For example: A simple averaging algorithm can be implemented by buffering N samples, adding them together and then dividing by N. If you cleverly select N to be a power of 2, then the division turns into a simple shift instruction.
Oh, and in case someone gets the bright idea of using this design themselves, be aware that the accelerometer used is limited to +/- 10G range when using the PWM outputs. And this is the high acceleration version of the part. The ADXL202 mentioned as an alternative in the article is limited to +/- 2G's.
But you probably already knew all this. :-)
Doug Sams wrote:

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Dave,
I'm in complete agreement. When I was selling FPGAs (up to 1999), the newest rage was IP cores such as processors. But an 80C31 core would use up most of a 40K gate part. 200 bucks to replace a 50 cent processor. (1999 dollars)
Anyway, there are certain things FPGAs do well that general purpose engines do not (including some special purpose DSP functions that general purpose DSPs do not) but I agree these examples were all for the "exercise" as you say.
As for filters, all real timers make their sliding windows 2^N samples long. We don't need no stinkin' divide :)
But it's still refreshing to see rocketry being addressed by high tech guys like Cypress and Altera even if the examples aren't very practical.
Doug
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My comments follow the quotation:

-------------------------------------
I've gotta jump in (though very late), as I've been working with FPGA-based designs for a number of years now. The latest FPGAs are way up in the multi-million equivalent logic gates. Cost per gate is way down and configuration PROMs are dirt cheap. How many processor cores would you like to stick in there? Maybe a few PCI bridges, too? No problem.
But I agree with you and Dave. FPGAs are dreadful power hogs compared to zero-power CPLDs and micro-power microcontrollers. FPGAs just don't stack up well in low-power applications, and the major FPGA manufacturers appear not to have much interest in such applications (though Lattice seems to have a family that seems headed in that direction).
On the other hand, if you need massively parallel processing, in a small package, mebee those FPGAs could stand a second look. Say, Synthetic Aperature Radar needs massive processing... anybody got a teeny-tiny SAR setup out there?
Dwayne Surdu-Miller SAROS #001
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Yes, the point of that regular feature in Design News is to use technology in a 'Rube Goldberg' sort of way.
GC
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I especially liked how they used a timer for apogee instead of calculating it.
RDH8
wrote:

in a 'Rube Goldberg' sort

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