EE's who do PCB Layout

Yes, I do everything too (circuit design, PCB layout, prototype build, testing, software). It seems to work OK. One advantage is that I can easily change things around to suit the layout, for example re-allocate microcontroller I/Os, without conferring with someone else each time.

We often let our layout guy pick pins, especially for mass connections, like a dozen ADCs connecting to one BGA FPGA. We'll just explain the general concept and let him do the massive amount of work to place the parts, pick the pins, and route the traces. He got 12

12-bit ADCs into a BGA, all on layer 1, with no vias or crossovers. It's beautiful, like a butterfly wing.

We also sit down with him, early in the design, and negotiate density, number of channels, placement, area, thermal issues, stuff like that. Sometimes he surprises us by commiting to get more on a board than we thought possible. Once we have a placement, sometimes we can assign pins at the initial schematic level, minimizing vias and layers. But he's just a few steps away, and we understand each other, so this sort of interaction works. If my only choice was an outside service, or a separate department, I'd be a lot more likely to do it myself.

John

I worked my last year in high school and freshman year in college as a pcb layout artist (back in 'dem red/blue tape and donuts days) and actually enjoy the layout as much as the design. Besides, there are always minor design improvements I can make on the fly in the layout process.

Jim

I do my own when our layout guy is either swamped or I'm convinced that the layout is critical enough that once you sum up the total time it'll take him plus my own time, it's significantly longer than if I just did it myself.

The process you describe -- someone other than the EE does the layout, the EE checks the results, iterations occur as necessary -- is pretty standard in most companies, especially those of significant size. You're right to notice some of the inherent inefficiencies in this process, but this has to be balanced with the fact that multiple bodies working on the same problem generally will finish in noticeably less time than one working alone (although certainly not in 50% of the time for anything much more complex than, e.g., breaking rocks :-) ) and also -- from the financial point of view -- the EEs generally cost a company more than the layout guys.

Hence my personal "policy" above of letting the layout guy do it when "reasonable" -- obviously a subjective call. This is largely influenced by how good your PCB guy is, and how well you communicate with them. While Joerg seems to have found himself a really good layout person, my experience hasn't been as good and most of the guys I've worked with had relatively little understanding of how, e.g., high-frequency analog or RF "works" (most of them generally had two-year degrees, although these days I very much doubt that most BSEEs fresh out of college are any better).

You'll probably have a better shot at convincing your boss to let you do your own PCBs if you're working on analog, RF, or switching power supply designs -- with those designs it's a lot easier to demonstrate that layout is much more critical than some "generic" digital board (e.g., microcontrollers) where even really sloppy layout still tends to work.

I spent a summer working as an intern at a Big Company (hundreds of millions per year revenue, thousands of employees) that had an entire layout

*department*, and unfortunately their "process" was so heavily oriented towards high-volume (often overseas) manufacturing -- implying lots of documentation, many reviews, etc. -- that for prototyping purposes the engineering department I was with simply used freebie software from, e.g., ExpressPCB! This was *much* faster AND cheaper (since the cost of layout was still charged backed to engineering, of course) than going through the layout department, but also quite sad that the company had become so segmented and political that the EEs just wanting to build a stupid prototype weren't "allowed" to use the fancy software the layout department had (the question of course being then how the software licenses would be paid for...).

---Joel

He probably does, but you might grossy overestimate how many "good PCB layout engineers" actually exist out there, especially if you are in Podunk, Nowhere. :-)

I just figured that I'm one of the few doing everything myself. We don't have Sole-Layouters here, or I haven't heard of them.

Rene

That can be especially gratifying when using a fully integrated CAD where a change in layout flows back to the schematic. "Oh, let's use singles gates instead."

Although me and my layouter have also easily done that, using totally different CAD software.

You were lucky you were allowed to. A similar sized notionally high quality oriented company I spent some time in didn't do prototypes, having spent tens of thousands per seat on Cadence design software engineers were supposed to simulate their designs avoiding the need for prototypes.

The layout process was as a (notional) quality enforcement mechanism. No layout would be started without around 16 signatures on a check list. Project manager, quality control, component engineer, CAD library engineer, drawing standards engineer, PCB layout engineer, reliability engineer, thermal engineer, environmental engineer, safety engineer, EMC engineer and more I don't remember. When you need signatures from 16 people at least one is bound to be on holiday or off site for a fortnight. Even when you got everything right no PCB would ever start layout without a 2 week delay.

Most better layout tools will also automatically swap (equivalent) gates and pins if asked to do so; I've found this a very nice little time saver when you're after a "clean" layout.

I do find the single-gate TinyLogic parts quite attractive, though...

It was a little bit of a skunkworks projects -- hence the reason they were using free software rather than one of the inexpensive options.

I've spent a lot of time trying to make it clear to managers (those without "hard" engineering backgrounds) that there's a *huge* difference between the software, hardware, and procedures needed for *prototypes* vs. that for

*production* and that while there may be some correlation between how much you spend on a simulator and how many prototypes you need to build, there's an even bigger correlatoin with who you hire to get the job down. :-) I'm heartened that those around here who appear to be quite good at circuit design -- folks like Joerg and John Larkin -- still seem to do plenty of measurements on prototypes and don't expect that a fancy simulator is going to eliminate the need for them entirely. (There are folks like Jim Thompson here who probably has plenty of "1st cut" design successes, but he gets fab models for transistors pre-simulation and then probably extracted netlists with parasitics included prior to fab -- something of a "leg up" there!")

---Joel

... and when you aren't available next time this board has a major spin? Is any of that information (currents, trace frequencies, special grounding requirements) captured in the schematic, preferably in the form of constraints?

Someone previously mentioned that it might be much more efficient for the engineer to layout the board. I strongly suspect it depends on the size and complexity of the board. The layout guys at my employeer (smallish telecom equipment provider) are REALLY good, but the density is such that it still takes them two to three weeks. That's a lot of time the EE could be doing something more productive for the company (like working on FPGA code so that when the board comes back from fab, you can fire the damn thing up!).

Of course, this only works if the layout guys are good. And even if they are, there is stuff you double check anyway. And as others have mentioned, they know the latest on the trade, and the tricks of the trade. It just doesn't seem like a good use of the EE's time to place a couple thousand 0402 resistors. If they need to be someplace special, put a constraint on them. How else will you double check it (even if you did it yourself)?

Marc

Agreed.

Count yourself lucky. :-)

But how many designs truly have a couple thousand resistors more or less individually positioned? Most such large projects are really just repeating a particular section multiple times, and any decent layout guy will layout a single section and then let his tool automatically group and route the other sections.

Many companies don't have a "flow" that supports the use of constraints. :-(

I work in power electronics as well. Power supplies are layout critical. One sensitive trace from the control system running under a noisy area and you will NEVER get the supply to work properly with that layout.

I have a layout department at my company as well. If the layout is critical - either do it youself or do a lot of hand holding with the layout person to get it right. In my experience, the only way for one person to layout a critical pcb is to have detailed knowledge of the design. That means the design engineer.

In some places with bypass capacitors, I'll try to create some trace to trace capacitance.. Dunno if it helps...

I haven't done trace resistors yet. I'm afraid a squiggly pattern is just more area to get induced currents from nearby power inductors.

D from BC

I took the statement kinds' tongue in cheek. Do you think he was being serious?

Jim

Who can tell ?

Management types certainly believe that kind of thing. Been there, done that, had to fix it.

Graham

Pretty much all allow gate swaps even across devices. Some go a lot farther: You can decide to split an inverter six-pack into singles if that prevents you from having to go to two more layer. Or go to a discrete solution if you find the logic chip version somehow doesn't pan out.

Yes. But a bit costly.

I wouldn't let a layout guy do PCB layout for power electronics, low noise analog, or RF. Anything else I have had good luck with. Trying to document the requirements for switching supplies, inverters, etc.. is just about impossible. Both creepage requirements between different parts... and the big one, _loop area_ of high dI/dt circuits is often lost on layout people.

The intergrated suites, yes, but if you're using, e.g., PADS layout with just a netlist for input (a not-at-all uncommon flow), it has no knowledge of what's "swappable" to begin with, so you end up having to do it back on the schematic and exporting the netlist again. This can takes long enough that some layout guys just don't bother; they'd rather add some more vias and have some ugly traces.

That's rather nice -- I take it Eagle does this?

Indeed; it's almost surprising that some Asian company hasn't come out with a line of single-gate ICs selling them for pennies in the thousands. Especially since they could use older, slower fab processes -- I'm almost never looking at TinyLogic for speed, yet that seems to be one of the main sales points you get about them. (Not that speed is bad, just that for every 7Z00 sold, I imagine under 10% actually require the speed provided.)

---Joel