external SRAM tutorials?

Hi Alex,

Which processor are you using ??

If the processor needs a latch for the memory interface, then the lower address bits and the data buss share the same pins.

Do you have any data sheets of the processor you would like to study ?? This is the best source of information.

Look over the timing diagrams. Relate the signal ( address or data ) to the location in time on the timing diagrams. Its not rocket science to even a raw beginner will pick it up easily.

hamilt> Are there any tutorials on using/accessing external SRAM? I don't want

A logic diagram of a latch is several D-type flip-flops with their clock inputs tied together. The input values are saved in the outputs when the clock input is toggled.

There could be a couple of reasons why you would need one (ISTR the

8048 multiplexed address/data bus needs one for etrernal RAM), and in some circumstances you would not need one.

Perhaps you need a logic tutorial to learn about inverters and nand gates and such, and how these can be connected to make flip-flops, latches, encoders, decoders, memories and such. There may be a TTL or CMOS tutorial or set of slides for a college class on the web. Failing that, get a textbook on digital logic, or the TTL Coolbook or CMOS Cookbook.

------------------ Sure. But you need to tell us what you're using it for. Here's a thumbnail scketch of SRAM:

It is a memory box with address input pins, and data in/out pins, and it has power (Vcc +5V) and Ground (GND) and it has three other pins, typically, /CE and /WE and /OE. Now /CE is chip enable, and the "/" (or a bar over the "CE") means that an "active-LO" logical signal enables the chip, that is "/CE" means "active-LO chip enable".

So likewise, "/OE" means active-LO output enable, which means that it makes the data pins into outputs, where otherwise they would be tristated (like disconnected), and also likewise "/WE" means "active-LO Write Enable", which means that when you pull /WE pin LO, the data-byte on the data pins gets written to whatever address location is set by the binary address number represented by the address states of the addreee pins.

To use SRAM, or Static Random Access Memory, all you do is set an address number in binary on the address pins, then set the /CE LO to enable the chip, and then:

Read the Data byte previously written to that address by setting the /WE = HI, and with the /OE set LO.

OR

Set an external data byte across the Data pins, and Write the Data byte to that address by setting /OE HI and the /WE LO.

And Remember: When you first power up the chip, all address locations in the memory have only random values.

The best way to do this is to use octal latches (74HCT.. or ..LS374/574) on the address lines and another to control the three control lines, and use a tristate data bus driver (74LS.. or ..HCT245) on the data lines, and then control the direction of data flow using the direction pin of the '245 in concert with the /WE and /OE lines.

Get the PDF databook file for the SRAM and these other chips and note the states and the timing diagrams for what pin has to change value for the read and write functions, and the timing considerations. Using it slowly for experimental purposes can be done with pushbuttons and switches using hex inverters or buffers and resistors and LEDs to display their states.

-Steve

Mainly curiosity. I've done a lot of projects with microcontrollers (PIC), including 2 psuedo-robots (currently working on a 3rd...as of yet, they don't actually do much though), and maybe for future projects, I'll have a need for some "serious" storage space. :)

/CE is the same as /CS (chip select), right?

Gotcha there.

Gotcha.

OK, so, the octal latch...That lets me use 1 set of 8 I/O pins for both parts (upper and lower bytes) of the address? I bought one while I was out at radioshack, just for S&Gs...and thats what it looks like from the table on the back (but it's a 573...will still work, right?).

I have a couple of 245s around here somewhere...Are they really neccessary? Or can I just tie the data lines directly to my MCU, and switch to input/output as needed?

Well...as of yet, I haven't found datasheets on any of the SRAMs I have layin around (they're old...from a 166mhz 486 that no longer functions). I'm going to start searching shortly, however, and see if I can get any of them to work. Likely I won't be using pushbuttons or anything...just a PIC and one of my 7 segment display boards.

Thanks for the info (and any more info you can give me! lol!)

-Alex

----------------- Yes, called /CE (chip enable) on some, and /CS (chip select) on others. Operates the output tristate data bus driver enable.

------------------- The 573 is a transparent latch, meaning the LE must be high to pass data through to the outputs, and when LE goes LO, it retains the last available 8 data states on its eight outputs.

The 574 is importantly different, it is not transparent, and only latches data on the edge of the clock.

---------------------- A 245 is a bidirectional bus driver, a 244 is sufficient in one direction, but the 245 is used to arbitrate a bidirectional data bus.

What are they?

------------------- Sure, lots of fun. Even more fun can be had trying to figure out how to do complex tasks with nothing but glue logic, it is a crucially important teacher of the talent of digital design.

---------------- Sure.

-Steve

Not sure, to be honest. They're big. They're ugly. Most of them are not likely to have datasheets even in historical archives! LOL. They're all DIP, too. I have 25-30 OLD SIMM memory modules, but all the chips are surface mount, and I don't feel like putzin around with it. Lemme go do a quick search, and see what I can come up with.

28 pin - UM61256AK-12 (9640G MA1258) x1 - some kind of SRAM by UMC, no datasheet

W24257AK-15 (95240) x1 - (32k sram from Winbond) Actually found a datasheet for this one! (15ns 32k x 8 high speed static ram)

32 pin - GLT751208-15T x4! - (searchdatasheets.com has this one, but i'm not paying 50 bucks to get in! seems to be the only place)

20 pin - M5M44256BP x2 - (256k x 4bit, 70 ns, 20 pin DRAM dip - Mitsubishi. but couldn't find any datasheet, not SRAM, but might be usefull regardless)

Thats just off of the 2 MBs I have handy...I've got 2 boxes full of old circuit boards from broken electronics/computers/peripherals.

If I can manage to read and write to ANY one of these chips, I'll be more than pleased with myself :P

Dunno how realistic that will be, with a 20mhz MCU (or maybe it'll be more than sufficient...haven't played around with anything like this before!)

That's good, you can use regular sockets and stuff.

You could do the refresh that the DRAM's need with any microcontroller, but it's more trouble than using static RAM. You're better off not bothering with DRAM's unless you really need the larger memory size they have.

The 61256 resembles a standard part number, earlier parts in the series were 6116 (2kx8) and 6164 (8kx8), so this is surely a 32kx8 chip. Googling for +61256 +RAM brings up a bunch of pages - here's a relevant one:

don't understand much on that page, but about two-thirds down is a diagram for four devices, the legend shows the third one in blue is a

61256. It also shows how the pinouts for earlier chips are similar - I recall this was a JEDEC standard, so you could change do different size RAM or EPROM chips and only have to change a very few jumpers, as it seems the text describes.

Try googling for the basic numeric part of the number, as I did above. These are usually made by several manufacturers, with the letters indicating manufacturer and case/lead type, and the numbers like -15 indicating speed.

I bet that's a standard 62256.

------------------------ Also I bet it's the same pinout. JEDEC pervades.

--------------------------- I bet you can find this elsewhere. Try the manufacture.

-------------------- Those are DRAMs.

-------------------------------- Look for 6116, 6264, 62256, xx128 etc.

-------------- That won't be hard, that's a minimal exercise.

----------------- SRAM is not always that fast, but it's not hard to accomodate it.

-Steve