Which is what I said in the part you snipped.
Not correct read the spec. In order to keep the average level at zero, if +ve stretched bits are in use then the period of the -ve part of the
0 data bits are extended so as to average the DC back to zero between stretched bits, that is why 0's are allowed to have different length -ve and +ve transitions. However, to the motor the fast -ve bits are are not seen as well due to the Low pass characteristics of the motor, so the motor sees a net +ve (or everything the other way around if you are reversing and using -ve stretched bits).Jeff