I keep reading in signal integrity books that it's not the frequency that causes problems, it's more the rise time. I know the definition of rise time, but I don't know how to get it. Does it have to be measured?, in which case you don't know what it is in advance. Is it calculated from the data sheet taking your frequency into account? Any help would be appreciated.
If you're willing to describe the model with just one time constant, there's a simple relationship between rise time Tr (seconds) and bandwidth BW (Hz):
Tr * BW = 0.38
Proof is a short exercise that begins with definition of Tr.
Imagine a digital system with a 1 Hz clock, but using ECL100k parts (or other similarly fast CMOS family parts). The clock might be ticking at 1 per second, but the rise time of those clock edges are sub-nanosecond, which contain substantial energies well past 5 GHz (0.35/500 ps -> 7th harmonic, 9th harmonic, etc.) (I use 0.35, for Gaussian systems, 0.38 is more conservative, but OK, too). So what is the system bandwidth? 1 Hz or 5+ GHz? Clock frequency and rise-time are independant! In this example, which is the one that you have to worry about for EMI? The rise time.
Rise time for a particular family of logic should always be given in the datasheets. Sometimes it is listed in the "general" section of a databook for the entire family, but lately I've seen it listed for most individual components in the datasheets. In some FPGAs the rise times are programmable.
HTH, Tom P.
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