These numbers are characteristic dimensions of features (DRAM half-pitch, etc.). Essentially, you can think of these numbers as the gate width.
There does not seem to be any reason not to be able to make things this small. The big problem is the on-chip wiring. About now, there is about 9 layers of thin, skinny copper wiring on top-of-the-line chips (I say top-of-the-line in terms of manufacturing acheivement, not performance).
At some point, you would be making tiny transistors buzzing away like crazy that are farther apart from each other than was the case in the previous generation, because the wiring would limit the performance too much if they were spaced closer together. The cost advantage of puting more transistors per unit area would disappear, and the cost would go up fast.
This is why people are looking at 3D ICs and such: interconnection.
---> Insert shameless plug for the article I wrote in the March 2004 issue of IEEE Spectrum. The money keepers need to understand this stuff before the engineers have a chance to do what they need to do.
Electronics