Re: Gates

On Fri, 18 Jul 2003 17:45:01 -0700, srgrimm wrote:

no
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Steve, you probably remembered this backwards - IE, you can build an AND gate, or any other logic function, using nothing more than NAND gates [or NOR gates, for that matter].
- dan michaels =========================
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Like others are saying, it is not possible to use AND gates to create an inverter. However, depending on how time cricitcal your app is, you can use an NPN transistor and a couple of resistors in a common emitter configuration to create a quick and dirty inverter.
Use something like a 1K between 5V and the collector, and a 10K between your input and the base (the base resistor value will depend on the base current recommended for the transistor you use. Ground the emitter.
The big disadvantage here is that at a high enough frequency the transistor will begin to act like a capacitor (it will add a slope to the low/high transistion.) Depends on what your motive is (parts on hand, cost, etc..)
Hope that helped, Scott

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srgrimm wrote:

Yes, certainly, as long as you accept using an external pullup resistor and don't mind blowing a whole package on one gate. Best to use symmetrical CMOS (eg - HC, not HCT).
Gerry
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Gerry,
Could you explain your circuit to us? Since I think it's impossible, it would be cool to learn a new way to make a nend gate. Please enlighten us.

--
- Alan Kilian <alank(at)timelogic.com>
Bioinformatics Applications Director, TimeLogic Corporation
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Hi
That's easy, you loop one gate back on itself to form a bistable, stack two more to delay the new data and set up a race hazard to store what the line used to be in the flop thus forming an inverter.
I don't think I need explain more because of course you're right, it is completely impossible. But just for a moment there, did you wonder?
best regards
Robin G Hewitt
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Yeah . You had me imagining the circuit just you you did...LOL

two
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Alan Kilian wrote:

Sure Alan, the technique simply uses, along with the normal gates from an AND gate package (call it package A), another entire AND gate package (call it package B) as a single inverter. This is inverter configuration is done all the time with CMOS and works especially well with HC (74HC08A 2-input AND, for example), since in practice they will output a nice low, down to about 0.9V or less. To build a NAND, you then connect in series a NAND gate from package A, the inverter (package B) and another NAND gate from package A acting as a non-inverting buffer, since the inverter will have a high-impedance output. The inverter's pullup should be about 100K to 1 megohm and you'll need another 100K-1M for an input series resistor because of the clamp diodes.
Gerry

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OOPS! Lets try again - NAND should have been AND, as below.
Sure Alan, the technique simply uses, along with the normal gates from an AND gate package (call it package A), another entire AND gate package (call it package B) as a single inverter. This is inverter configuration is done all the time with CMOS and works especially well with HC (74HC08A 2-input AND, for example), since in practice they will output a nice low, down to about 0.9V or less. To build a NAND, you then connect in series an AND gate from package A, the inverter (package B) and another AND gate from package A acting as a non-inverting buffer, since the inverter will have a high-impedance output. The inverter's pullup should be about 100K to 1 megohm and you'll need another 100K-1M for an input series resistor because of the clamp diodes.
Gerry

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Robin G Hewitt wrote:

OK - take any CMOS non-inverting gate package, like an 'HC08. Connect all inputs together and call it input. Connect all the original output pins together and connect to ground. Connect ground pin to ground. Connect Vdd pin to +5V through a 1 Meg pullup. The Vdd pin is the new "output" of this inverter configuration. When the input is LO, the "output" is HI because CMOS draws no quescent current to speak of so the voltage at Vdd is the same as the +5V supply. When the input is HI, the original output pins try to go HI, but because of the short to ground they simply drive current into the short. The current flows into Vdd through the 1 Meg pullup resistor and causes the Vdd level to drop. It stops dropping when the Vdd value is so low that the p-FET on resistance at the original output pins increases to the point where no further current can be driven. For 'HC, this is about 0.9V, for 'AC, about 0.5V. That voltage value is the LO level at the "output". You could build an AND gate this way directly, but adding a CMOS AND gate before it and a CMOS buffer (using an AND gate) after it makes it more useful (if you can say that about this configuration ;>). Hope this is clear, sorry for rushing the previous post - had a cat go into labor!
Gerry
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inputs
and
Hi Gerry
So you wire the chip like one snogging girt transistor? Thank goodness, I was really worried I might have been missing a trick all these years. If I ever find myself cast away on a desert island without inverters, I will be sure to try it :o)
An excellent, if slightly unorthodox, contribution.
My best regards to you and your cat
Robin G Hewitt
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